A lead frame is usually used as a chip carrier for mounting a semiconductor chip thereon to form a semiconductor package. The lead frame comprises a die pad and a plurality of leads around the die pad. After the semiconductor chip is attached to the die pad and is electrically connected to the leads by bonding wires, an encapsulant is formed to encapsulate the chip, the die pad, the bonding wires and inner portions of the leads, thereby completing the semiconductor package.
Various types of lead-frame-based semiconductor packages have been developed such as QFP (Quad Flat Package), QFN (Quad Flat Non-leaded) package, SOP (Small Outline Package), DIP (Dual in-line Package) and so on. In order to improve the heat dissipating efficiency and reduce the size of the semiconductor package, the QFN package with an exposed die pad is mostly favorable at present.
The QFN package is characterized in not having outer leads, unlike the QFP using the outer leads for electrically connecting an external device, such that the size of the QFN package can be reduced. As shown in FIG. 1 (PRIOR ART), bottom surfaces of a die pad 11 and leads 12 of a lead frame in the QFN package 1 are all exposed from an encapsulant 15, such that heat produced by a semiconductor chip 13, which is mounted on the die pad 11 and is electrically connected to the leads 12 via bonding wires 14, can be effectively dissipated out of the QFN package 1. The exposed surfaces of the leads 12 can be bonded to bond pads 100 of an external device such as a printed circuit board 10 via solder joints 16 to electrically connect the QFN package 1 to the printed circuit board 10.
However, the thickness of the lead-frame-based semiconductor package cannot be further reduced as having to count the thickness of the lead frame. Since profile miniaturization of a semiconductor product becomes more and more important, there is developed a semiconductor package without a chip carrier (customarily referred to as carrier-free semiconductor package), which desirably makes the thickness thereof smaller than the thickness of the lead-frame-based package.
FIG. 2 (PRIOR ART) shows a carrier-free semiconductor package disclosed in U.S. Pat. No. 5,830,800. In the semiconductor package, a plurality of plated pads 21 are formed on a copper carrier (not shown) according to a predetermined circuit layout. Each of the plated pads 21 comprises Au/Pd/Ni/Pd layers and has a thickness of about 6 μm. Next, a chip 22 is mounted on the copper carrier and connected with bonding wires 23, and an encapsulant 24 is formed by a molding process. Then, the copper carrier is removed and the plated pads 21 are exposed. The carrier-free semiconductor package is thus completed, and can be electrically connected to an external device such as a printed circuit board 20 by bonding the exposed plated pads 21 to bond pads 200 of the printed circuit board 20 via solder joints 26.
Referring to FIG. 3 (PRIOR ART), however, as the QFN package or the carrier-free semiconductor package is directly attached to and abuts against the printed circuit board via solder joints 36 and by Surface Mount Technology (SMT), when forming the solder joints 36 by reflowing a solder material, if the amount of solder material or an attachment distance between the package and the printed circuit board is not precisely controlled, the adjacent solder joints may easily come into contact with each other and cause short circuit S, as shown in FIG. 3 (PRIOR ART).
During the fabrication processes, thermal stress may be produced between the package and the printed circuit board due to mismatch in Coefficient of Thermal Expansion (CTE) between materials of the package and the printed circuit board. The thermal stress is directly proportional to the CTE mismatch and is inversely proportional to the height of the solder joints. As the foregoing package is bonded to the printed circuit board by SMT and through the solder joints only, due to the CTE mismatch between the package and the printed circuit board, significant thermal stress is exerted to the solder joints. Such thermal stress is directly proportional to ((α2−α1)/ΔT·δ1)/h, wherein (α2−α1) represents the CTE difference between the package and the printed circuit board, ΔT represents the largest temperature difference between the package and the printed circuit board, δ1 represents the distance from the center of the package to the farthest solder joint, and h represents the height of the solder joints. In the foregoing package, the solder joints 36 as having an extremely low height h between the package and the printed circuit board would suffer very high thermal stress, which not only reduces the fatigue life of the solder joints 36 but also leads to cracking of the solder joints 36, thereby severely degrading reliability of the electronic product. On the other hand, if increasing the amount of solder material and the height of the solder joints, the adjacent solder joints may easily come into contact with each other and cause short circuit in the case using an excess amount of the solder material or failing to precisely control the attachment distance between the package and the printed circuit board.
Therefore, the problem to be solved here is to provide a semiconductor package and a fabrication method thereof, which can eliminate the above drawbacks in the prior art.